1. Field of the Invention
The present invention relates to a gate signal line driving circuit and a display device using the gate signal line driving circuit, and more particularly to a technique which realizes the suppression of noises and the prolongation of lifetime in a gate signal line driving circuit.
2. Description of the Related Art
Conventionally, for example, with respect to a liquid crystal display device, there may be a case where a so-called shift register built-in method is adopted. Here, this method is a method in which a shift register circuit provided to a gate signal line driving circuit for scanning gate signal lines is formed on the same substrate as thin film transistors (hereinafter referred to as TFTs) which are arranged in pixel regions of a display panel. A shift register circuit according to the related art is disclosed in JP 2007-95190 A.
In each one of a plurality of basic circuits which are included in a shift register circuit provided to a gate signal line driving circuit, within one frame period, only during a gate scanning period, in which a gate signal is outputted from the basic circuit to a gate signal line (hereinafter referred to as “signal HIGH period”), a HIGH voltage is outputted to the gate signal line as a gate signal Gout, and during a remaining period (hereinafter referred to as “signal LOW period”), a LOW voltage is outputted to the gate signal line as a gate signal Gout.
FIG. 11 is a schematic view simply showing the configuration of a basic circuit of a shift register circuit according to a related art. The basic circuit of the shift register circuit includes a LOW voltage applying switching element SWA which outputs a LOW voltage to the gate signal line corresponding to the signal LOW period, and a HIGH voltage applying switching element SWG which outputs a HIGH voltage to the gate signal line corresponding to the signal HIGH period.
A LOW voltage line VGL is connected to an input terminal of the LOW voltage applying switching element SWA. To enable the stable outputting of the LOW voltage during the signal LOW period with respect to the gate signal Gout of the basic circuit, the LOW voltage applying switching element SWA is turned on in response to the signal LOW period so that a LOW voltage which is a voltage of the LOW voltage line VGL is outputted. Further, the LOW voltage applying switching element SWA is turned off in response to the signal HIGH period. During a period in which the LOW voltage applying switching element SWA is turned on, a HIGH voltage is applied to a switch of the LOW voltage applying switching element SWA.
A basic clock signal CLK is inputted to an input terminal of the HIGH voltage applying switching element SWG. To enable the outputting of the HIGH voltage during the signal HIGH period with respect to the corresponding gate signal line, the HIGH voltage applying switching element SWG is turned on in response to the signal HIGH period so that a voltage of the basic clock signal CLK is outputted. Here, the basic clock signal CLK assumes a HIGH voltage during the signal HIGH period. Further, the HIGH voltage applying switching element SWG is turned off in response to the signal LOW period so that the basic clock signal CLK is interrupted, or is not outputted. A HIGH voltage is applied to a switch of the HIGH voltage applying switching element SWG during a period in which the HIGH voltage applying switching element SWG is turned on, and a LOW voltage is applied to the switch of the HIGH voltage applying switching element SWG during a period in which the HIGH voltage applying switching element SWG is turned off.
To the switch of the HIGH voltage applying switching element SWG, a switching signal supply switching element SWB which supplies a LOW voltage in response to the signal LOW period is connected. The LOW voltage line VGL is connected to an input terminal of the switching signal supply switching element SWB. The switching signal supply switching element SWB is turned on in response to the signal LOW period so that a LOW voltage is applied to a switch of the HIGH voltage applying switching element SWG. Further, the switching signal supply switching element SWB is turned off in response to the signal HIGH period. During a period in which the switching signal supply switching element SWB is turned on, a HIGH voltage is applied to a switch of the switching signal supply switching element SWB.
FIG. 12 is a circuit diagram of a basic circuit of a shift register circuit according to a related art. As shown in the drawing, a transistor T6 provided to a LOW voltage applying switching circuit 211 corresponds to the LOW voltage applying switching element SWA. A node N2 is held at a HIGH voltage in response to a signal LOW period, and a LOW voltage of a LOW voltage line VGL is outputted from an output terminal OUT as a gate signal Gn.
Further, as shown in the drawing, a transistor T5 provided to a HIGH voltage applying switching circuit 212 corresponds to the HIGH voltage applying switching element SWG. A node N1 assumes a HIGH voltage in response to a signal HIGH period, and a voltage of a basic clock signal CLK1 inputted from an input terminal IN1 is outputted from the output terminal OUT as a gate signal Gn.
Further, as shown in the drawing, a transistor T2 provided to a switching signal supply switching circuit 213 corresponds to the switching signal supply switching element SWB. A node N2 is held at a HIGH voltage in response to the signal LOW period, and a LOW voltage of a LOW voltage line VGL is applied to the node N1.